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Displaying html from Mysql Database Error

Posted: Tue Sep 22, 2009 9:18 am
by wolfnipplechips
OK, this is really strange - it's kind of a crossover php/html issue, so apoligies if its in the wrong area.

I have the following page, which is populated from a mysql table. Except it's deciding not to show any of the <li>'s or <ul>'s - even though it's all stored correctly in the database. For example, half way down the page in a "course agenda" section, looking at the source code for this section will show that there is a whole load of formatting it's choosing not to display.

http://www.testesperan.co.uk/frontend_s ... ourseID=48

Does anyone have any suggestions as to what going wrong.

Thanks in advance
Phil

Re: Displaying html from Mysql Database Error

Posted: Tue Sep 22, 2009 9:26 am
by Eric!
Hey! I used to do some vhdl and verilog design!

Anyway it wasn't immediately apparent to me where the ton of formatting was missing. Can you post the section of code and give examples of html that is not correct? please use the proper

Code: Select all

tags.

As a guess are some of the format strings escaped when stored in your database then not unescaped when displayed?

Re: Displaying html from Mysql Database Error

Posted: Tue Sep 22, 2009 9:34 am
by wolfnipplechips
Hi there,

Thanks for the reply.

The html stored in the database is fine, as viewing the source the browser demonstrates.

Taking "course agenda" for example, here is what is stored in the database, except for a bit of mess at the bottom, nothing wrong that I can see...

Code: Select all

<p><span class="bodytext"><span class="bodytextbold">Days 1-2 Language Basics and Application Overview</span><br />
</span></p>
<ul>
    <li><span class="bodytext">VHDL application overview</span></li>
    <li><span class="bodytext">VHDL language introduction     </span></li>
    <li><span class="bodytext">Design units and main language concepts         </span>
    <ul>
        <li><span class="bodytext">Signals and drivers</span></li>
        <li><span class="bodytext">Pre-defined and user defined types</span></li>
        <li><span class="bodytext">Standard logic</span></li>
        <li><span class="bodytext">Array, enumerated and record types</span></li>
    </ul>
    </li>
    <li><span class="bodytext">Logical and relational operators, concatenation and array slices</span></li>
    <li><span class="bodytext">Processes and sequential statements</span></li>
    <li><span class="bodytext">Concurrent statements and equivalent processes</span></li>
    <li><span class="bodytext">Simulation execution, sensitivity lists and wait statements</span></li>
    <li><span class="bodytext">Variables and variable use</span></li>
    <li><span class="bodytext">Arithmetical operators, overloading and arithmetic packages</span></li>
    <li><span class="bodytext">Overview of coding styles for testbenches, RTL and behavioral code     </span>
    <ul>
        <li><span class="bodytext">Datapath and control examples of behavioral and RTL modeling</span></li>
    </ul>
    </li>
    <li><span class="bodytext">The synthesis process and methodology overview</span></li>
</ul>
<p><span class="bodytext"><br />
<span class="bodytextbold">Day 3: Synthesis Coding Styles in Depth</span><br />
</span></p>
<ul>
    <li><span class="bodytext">RTL coding styles and guidelines for efficient synthesis     </span>
    <ul>
        <li><span class="bodytext">Describing combinatorial logic</span></li>
        <li><span class="bodytext">Inferring registered logic</span></li>
    </ul>
    </li>
    <li><span class="bodytext">Simulation, synthesis and optimization of arithmetic operators</span></li>
    <li><span class="bodytext">Coding styles for efficient hardware synthesis</span></li>
    <li><span class="bodytext">FSM's and state vector encoding</span></li>
    <li><span class="bodytext">Synthesis of variables</span></li>
    <li><span class="bodytext">Modeling timing in VHDL     </span>
    <ul>
        <li><span class="bodytext">Delay modeling, gate level simulation and VITAL</span></li>
    </ul>
    </li>
</ul>
<p><span class="bodytext"> <br />
<span class="bodytextbold">Day 4-5: Language Constructs, Coding Styles & Strategies for Verification</span><br />
</span></p>
<ul>
    <li><span class="bodytext">Procedures and functions     </span>
    <ul>
        <li><span class="bodytext">Overloading,type qualification and resolution functions</span></li>
    </ul>
    </li>
    <li><span class="bodytext">Generics, generates and blocks</span></li>
    <li><span class="bodytext">Unconstrained, type indexed and multi-dimensional arrays</span></li>
    <li><span class="bodytext">Types, sub-types, closely-related types and type conversions</span></li>
    <li><span class="bodytext">Coding styles and strategies for generating test stimulus     </span>
    <ul>
        <li><span class="bodytext">Creating clocks and resets</span></li>
        <li><span class="bodytext">Reading and writing data using file I/O</span></li>
        <li><span class="bodytext">Script driven testbenches</span></li>
        <li><span class="bodytext">Data and message outputs for efficient verification</span></li>
        <li><span class="bodytext">Result visualization</span></li>
    </ul>
    </li>
    <li><span class="bodytext">Design organization and management     </span>
    <ul>
        <li><span class="bodytext">Options and strategies for using configurations</span></li>
        <li><span class="bodytext">Compilation, elaboration, initialization and simulation</span></li>
        <li><span class="bodytext">Efficient use of packages</span></li>
    </ul>
    </li>
    <li><span class="bodytext">VHDL2006 Updates     </span>
    <ul>
        <li><span class="bodytext">New operators</span></li>
        <li><span class="bodytext">Statement enhancements</span></li>
        <li><span class="bodytext">Array declarations and assignments</span></li>
        <li><span class="bodytext">Sized and signed literals</span></li>
        <li><span class="bodytext">New verification features</span></li>
        <li><span class="bodytext">Property Specification Language (PSL) assertions</span></li>
        <li><span class="bodytext">Fixed/floating-point arithmetic packages</span></li>
    </ul>
    </li>
</ul>
<p><span class="bodytextbold">Appendices</span></p>
<ul>
    <li><span class="bodytext">Index of code examples</span></li>
    <li><span class="bodytext">Introduction to Property Specification Language (PSL)</span></li>
    <li><span class="bodytext">Index</span></li>
</ul>
<p><span class="bodytext"> <span class="bodytextbold"> Course Labs</span><br />
The labs have been designed to follow on from each other over the course of the training, building on code developed in each lab to create an overall design project.<br />
The first few labs get you familiar with the tools you are using and the basic steps involved in simulating and synthesizing a small design. Subsequent labs are based upon design modeling and verification issues that are typically encountered in a real world design project.<br />
<br />
The lab sessions include<br />
</span></p>
<ul>
    <li><span class="bodytext">Familiarization with simulation and synthesis tools</span></li>
    <li><span class="bodytext">Describing and verifying combinatorial logic</span></li>
    <li><span class="bodytext">Creating registered logic</span></li>
    <li><span class="bodytext">Using vector arithmetic packages</span></li>
    <li><span class="bodytext">Structural design and hierarchy</span></li>
    <li><span class="bodytext">Verification using visualization of results</span></li>
    <li><span class="bodytext">State machine design</span></li>
    <li><span class="bodytext">Verification using script driven, self-checking testbenches</span></li>
    <li><span class="bodytext">Integration and verification of a third-party IP model</span></li>
</ul>
<p>&nbsp;</p>
<p>&nbsp;</p>
<p><span class="bodytext">&nbsp;</span></p></span><br />
This is also visible when viewing the source in the browser - so nothing wrong there.

Why then is it not showing any of the bullet points etc on the actual page? STrange!

Re: Displaying html from Mysql Database Error

Posted: Tue Sep 22, 2009 9:39 am
by wolfnipplechips
Sorry, this is what is stored in the database (pasted the wrong code)

Code: Select all

<p><span class="bodytext"><span class="bodytextbold">Days 1-2 Language Basics and Application Overview</span><br />
</span></p>
<ul>
    <li><span class="bodytext">VHDL application overview</span></li>
    <li><span class="bodytext">VHDL language introduction     </span></li>
    <li><span class="bodytext">Design units and main language concepts         </span>
    <ul>
        <li><span class="bodytext">Signals and drivers</span></li>
        <li><span class="bodytext">Pre-defined and user defined types</span></li>
        <li><span class="bodytext">Standard logic</span></li>
        <li><span class="bodytext">Array, enumerated and record types</span></li>
    </ul>
    </li>
    <li><span class="bodytext">Logical and relational operators, concatenation and array slices</span></li>
    <li><span class="bodytext">Processes and sequential statements</span></li>
    <li><span class="bodytext">Concurrent statements and equivalent processes</span></li>
    <li><span class="bodytext">Simulation execution, sensitivity lists and wait statements</span></li>
    <li><span class="bodytext">Variables and variable use</span></li>
    <li><span class="bodytext">Arithmetical operators, overloading and arithmetic packages</span></li>
    <li><span class="bodytext">Overview of coding styles for testbenches, RTL and behavioral code     </span>
    <ul>
        <li><span class="bodytext">Datapath and control examples of behavioral and RTL modeling</span></li>
    </ul>
    </li>
    <li><span class="bodytext">The synthesis process and methodology overview</span></li>
</ul>
<p><span class="bodytext"><br />
<span class="bodytextbold">Day 3: Synthesis Coding Styles in Depth</span><br />
</span></p>
<ul>
    <li><span class="bodytext">RTL coding styles and guidelines for efficient synthesis     </span>
    <ul>
        <li><span class="bodytext">Describing combinatorial logic</span></li>
        <li><span class="bodytext">Inferring registered logic</span></li>
    </ul>
    </li>
    <li><span class="bodytext">Simulation, synthesis and optimization of arithmetic operators</span></li>
    <li><span class="bodytext">Coding styles for efficient hardware synthesis</span></li>
    <li><span class="bodytext">FSM's and state vector encoding</span></li>
    <li><span class="bodytext">Synthesis of variables</span></li>
    <li><span class="bodytext">Modeling timing in VHDL     </span>
    <ul>
        <li><span class="bodytext">Delay modeling, gate level simulation and VITAL</span></li>
    </ul>
    </li>
</ul>
<p><span class="bodytext"> <br />
<span class="bodytextbold">Day 4-5: Language Constructs, Coding Styles & Strategies for Verification</span><br />
</span></p>
<ul>
    <li><span class="bodytext">Procedures and functions     </span>
    <ul>
        <li><span class="bodytext">Overloading,type qualification and resolution functions</span></li>
    </ul>
    </li>
    <li><span class="bodytext">Generics, generates and blocks</span></li>
    <li><span class="bodytext">Unconstrained, type indexed and multi-dimensional arrays</span></li>
    <li><span class="bodytext">Types, sub-types, closely-related types and type conversions</span></li>
    <li><span class="bodytext">Coding styles and strategies for generating test stimulus     </span>
    <ul>
        <li><span class="bodytext">Creating clocks and resets</span></li>
        <li><span class="bodytext">Reading and writing data using file I/O</span></li>
        <li><span class="bodytext">Script driven testbenches</span></li>
        <li><span class="bodytext">Data and message outputs for efficient verification</span></li>
        <li><span class="bodytext">Result visualization</span></li>
    </ul>
    </li>
    <li><span class="bodytext">Design organization and management     </span>
    <ul>
        <li><span class="bodytext">Options and strategies for using configurations</span></li>
        <li><span class="bodytext">Compilation, elaboration, initialization and simulation</span></li>
        <li><span class="bodytext">Efficient use of packages</span></li>
    </ul>
    </li>
    <li><span class="bodytext">VHDL2006 Updates     </span>
    <ul>
        <li><span class="bodytext">New operators</span></li>
        <li><span class="bodytext">Statement enhancements</span></li>
        <li><span class="bodytext">Array declarations and assignments</span></li>
        <li><span class="bodytext">Sized and signed literals</span></li>
        <li><span class="bodytext">New verification features</span></li>
        <li><span class="bodytext">Property Specification Language (PSL) assertions</span></li>
        <li><span class="bodytext">Fixed/floating-point arithmetic packages</span></li>
    </ul>
    </li>
</ul>
<p><span class="bodytextbold">Appendices</span></p>
<ul>
    <li><span class="bodytext">Index of code examples</span></li>
    <li><span class="bodytext">Introduction to Property Specification Language (PSL)</span></li>
    <li><span class="bodytext">Index</span></li>
</ul>
<p><span class="bodytext"> <span class="bodytextbold"> Course Labs</span><br />
The labs have been designed to follow on from each other over the course of the training, building on code developed in each lab to create an overall design project.<br />
The first few labs get you familiar with the tools you are using and the basic steps involved in simulating and synthesizing a small design. Subsequent labs are based upon design modeling and verification issues that are typically encountered in a real world design project.<br />
<br />
The lab sessions include<br />
</span></p>
<ul>
    <li><span class="bodytext">Familiarization with simulation and synthesis tools</span></li>
    <li><span class="bodytext">Describing and verifying combinatorial logic</span></li>
    <li><span class="bodytext">Creating registered logic</span></li>
    <li><span class="bodytext">Using vector arithmetic packages</span></li>
    <li><span class="bodytext">Structural design and hierarchy</span></li>
    <li><span class="bodytext">Verification using visualization of results</span></li>
    <li><span class="bodytext">State machine design</span></li>
    <li><span class="bodytext">Verification using script driven, self-checking testbenches</span></li>
    <li><span class="bodytext">Integration and verification of a third-party IP model</span></li>
</ul>
</p>

Re: Displaying html from Mysql Database Error

Posted: Tue Sep 22, 2009 10:18 am
by Eric!
I have to apologize in advance. I'm traveling and using a pda with limited tools so I can't test my suspicions. I did notice some oddly nested il tags like line 6 isn't closed until line 13. Also the ul tag is opened twice, once on line 3 and then line 7. I don't know these tags well enough to know how the browser renders them when this happens.

Do you have a style declared somewhere on the page for the il tag?

Re: Displaying html from Mysql Database Error

Posted: Tue Sep 22, 2009 12:06 pm
by kaszu
You don't see bullets and indentions, because by default UL and LI has margins, but you have CSS reset and #maincontentsub has style overflow: 'hidden';

Code: Select all

* {
    padding:0; margin: 0;
}
#maincontentsub {
    ...
    overflow: hidden;
    ...
}

Re: Displaying html from Mysql Database Error

Posted: Tue Sep 22, 2009 1:22 pm
by wolfnipplechips
Fantastic! Thanks for your help, I forgot there were two stylesheets.